1. Field of the Invention
The present invention generally relates to a circuit layout, in particular, to a method for calculating an optimal length of trace between adjoining bends in the circuit layout.
2. Description of Related Art
In common high speed digital circuits, due to the limitation of layout, two sub circuits or devices must be connected by a bent transmission trace on a single printed circuit board (PCB). FIG. 1A illustrates a layout of right-angle bend. In the right-angle wiring, the effective width of the bend in the transmission trace abruptly becomes wider, and the excess area of the bend may result in a larger equivalent capacitance. Therefore, the bend may cause the discontinuous impedance, and the impedance of the bend is reduced, which incurs a signal reflection phenomenon to some extent.
In order to solve the problem of the capacitive reactance caused by the 90 degrees right angle in the layout, usually the layout area at the bend is reduced. FIG. 1B illustrates a layout of a mitred bend. Through the mitred bend and a suitable degree of chamfering, the stray capacitance can be suppressed.
The layout in FIG. 1A is the most unsatisfactory, and generates the most reflection. The layout in FIG. 1B can suppress the stray capacitance caused by the excess area of the bend, and is a better layout. If the area of the PCB allows, an angle of 90 degrees can be replaced by two bends of 45 degrees. FIG. 1C illustrates a layout of a bend of 45 degrees. As compared with FIGS. 1A and 1B, FIG. 1C is the best layout, and is also most commonly used in the industry, but relatively occupies much area of the PCB. In order to save the area of the PCB, it is better to reduce a length L2 of trace between the two adjoining bends of 45 degrees. However, if the length L2 is too short, a severe signal superposition and reflection phenomenon is caused. Currently, it is hard to determine the shortest length of trace between the adjoining bends.